During the manufacturing of digital integrated circuits, a manufacturing defect may result in an unintentional resistive path between different signal nodes, between a signal node and a power supply node, or between a signal node and ground. One common test approach is to apply sequences of logical input signals and monitor the resulting output signals. As complexity grows, however, it becomes increasingly difficult to find an input signal sequence that correctly exercises all internal nodes of interest and that guarantees that an internal node fault will propagate to an output for detection. In addition, a node defect may not be detectable as a logical fault. For example, as a result of a resistive or shorted node, circuitry may simultaneously pull-up and pull-down the node. The result of the conflicting conductances may be an intermediate voltage that may or may not induce logic errors. Conflicting conductances may, however, result in a detectable increase in power supply current. For example, if a node is shorted to ground and a gate attached to the shorted node attempts to drive the shorted node to a supply voltage (or conversely, if a node is shorted to a supply voltage and a gate attempts to drive the shorted node to ground), the shorted node may cause a detectable increase in the current drawn by the integrated circuit. If the current change is detectable, the node fault may be detectable without having to propagate the fault to an output node. In addition, the node fault may be detectable even if no logical error is induced. Testing based on detecting an increase in power supply current is called quiescent current testing or IDDQ testing. For a collection of articles providing general background information, see Y. K. Malaiya and R. Rajsuman, Bridging Faults and IDDQ Testing, IEEE Computer Society Press, 1992.
Standard CMOS logic requires each input to be connected to the gate of both an nMOS and a pMOS transistor. Implementing a gate requiting a large "fan-in" (many inputs) using standard CMOS may require multiple levels of standard gates, each gate having a limited number of inputs. There are other gate designs, for example pseudo-nMOS gates, that require only one transistor per input. Pseudo-nMOS gates permit a reduction in the gate size, a reduction in the gate delay time (by implementing a logic function in a single level), and a reduction in complexity relative to standard CMOS gates but typically at the expense of an increase in power relative to standard CMOS. In complex integrated logic circuits, it is sometimes desirable to mix the types of logic gates, using pseudo-nMOS gates where appropriate for high fan-in and using standard CMOS gates for the remainder of the logic circuitry.
Quiescent current testing is typically limited to static logic circuitry in which there is negligible static current. In particular, IDDQ testing is especially useful for standard CMOS logic, which draws negligible current under static conditions. Pseudo-nMOS gates, however, inherently draw current even under static conditions. For example, pseudo-nMOS NOR gates typically have multiple nMOS logic switches between an output and ground and a single p-channel MOSFET load transistor between a power supply and the output, with the gate of the load transistor connected to ground. If the output of the pseudo-nMOS gate is high, there is no static current. If the output of the pseudo-nMOS gate is pulled low by one or more logic switches, current flows through the load transistor. The magnitude of this current is much greater than the magnitude of quiescent current for standard CMOS logic and may be on the same order as the current due to defective shorted nodes in standard CMOS logic. Therefore, quiescent current testing is typically impractical in a design including pseudo-nMOS gates. There is a need, in a logic system containing a mix of standard CMOS gates and pseudo-nMOS gates, to be able to use quiescent current testing for the logic system.